View EL5623IRZ-T7_1236622.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

(R)
EL5623
Data Sheet May 6, 2005 FN7507.1
Multi-Channel Buffer
The EL5623 integrates six channels of gamma buffers into a single device. The top three gamma channels in each device are designed to swing to the upper supply rail, with the other three designed to swing to the lower rail. The output capability of each channel is 10mA continuous, with 120mA peak. The gamma buffers feature a 10MHz -3dB bandwidth specification and a 9V/s slew rate. Packaged in the 16-pin TSSOP package, the EL5623 is specified for operation over the -40C to +85C temperature range.
Features
* Six gamma buffers - 10MHz BW - 9V/s SR - 120mA peak IOUT - 3 high side drivers - 3 low side drivers * 3.5mA supply current * Pb-free available (RoHS compliant)
Applications
* TFT-LCD monitors * LCD televisions * Industrial flat panel displays
Ordering Information
PART NUMBER (See Note) EL5623IRZ EL5623IRZ-T7 EL5623IRZ-T13 PACKAGE (Pb-Free) 16-Pin TSSOP 16-Pin TSSOP 16-Pin TSSOP TAPE & REEL 7" 13" PKG DWG. # MDP0048 MDP0048 MDP0048
Pinout
EL5623 (16-PIN TSSOP) TOP VIEW
VS+ 1 OUT1 2 OUT2 3 OUT3 4 OUT4 5 OUT5 6 OUT6 7 VS- 8 16 VS+ 15 IN1 14 IN2 13 IN3 12 IN4 11 IN5 10 IN6 9 VS-
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2004, 2005. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
EL5623
Absolute Maximum Ratings (TA = 25C)
Supply Voltage between VS+ and VS- . . . . . . . . . . . . . . . . . . . .+18V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . VS- -0.5V, VS+ +0.5V Maximum Continuous Output Current (VOUT1-6) . . . . . . . . . . 15mA Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
VS+ = +15V, VS- = 0, RL = 10k, CL = 10pF to 0V, and TA = 25C Unless Otherwise Specified CONDITIONS MIN TYP MAX UNIT
DESCRIPTION
INPUT CHARACTERISTICS (REFERENCE BUFFERS) VOS TCVOS IB RIN CIN AV CMIR Input Offset Voltage Average Offset Voltage Drift Input Bias Current Input Impedance Input Capacitance Voltage Gain Input Voltage Range 1V VOUT 14V IN1 to IN3 IN4 to IN6 OUTPUT CHARACTERISTICS (REFERENCE BUFFERS) VOH High Level Output Voltage (OUT1) High Level Output Voltage (OUT2-OUT3) High Level Output Voltage (OUT4-OUT6) VOL Low Level Output Voltage (OUT1-OUT3) Low Level Output Voltage (OUT4-OUT5) Low Level Output Voltage (OUT6) POWER SUPPLY PERFORMANCE PSRR IS Power Supply Rejection Ratio Total Supply Current Reference buffer VS from 5V to 15V 50 80 3.5 4.5 dB mA VS+ = 15V, IO = 5mA, VI = 13.5V, TO = 25C VS+ = 15V, IO = 5mA, VI = 1.5V, TO = 25C VS+ = 15V, IO = 5mA, VI = 0V, TO = 25C VS+ = 15V, IO = 5mA, VI = 15V, TO = 25C 14.85 14.8 13.45 14.9 14.85 13.5 1.5 0.15 0.1 1.55 .2 0.15 V V V V V V 0.992 1.5 0 VCM = 0V (Note 1) VCM = 0V 2 5 2 10 1.35 1.008 VS+ VS+ -1.5 50 20 mV V/C nA M pF V/V V V
DYNAMIC PERFORMANCE (BUFFER AMPLIFIERS) SR tS BW GBWP PM CS NOTES: 1. Measured over operating temperature range. 2. Slew rate is measured on rising and falling edges. Slew Rate (Note 2) Settling to +0.1% (AV = +1) -3dB Bandwidth Gain-Bandwidth Product Phase Margin Channel Separation (AV = +1), VO = 2V step RL = 10k, CL = 10pF RL = 10k, CL = 10pF RL = 10k, CL = 10pF f = 5MHz 5 9 500 10 6 50 75 V/s ns MHz MHz dB
2
FN7507.1 May 6, 2005
EL5623 Pin Descriptions
PIN NUMBER 1, 16 2 3 4 5 6 7 8, 9 10 11 12 13 14 15 PIN NAME VS+ OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 VSIN6 IN5 IN4 IN3 IN2 IN1 Positive supply voltage Output gamma channel 1 Output gamma channel 2 Output gamma channel 3 Output gamma channel 4 Output gamma channel 5 Output gamma channel 6 Negative supply Input gamma channel 6 Input gamma channel 5 Input gamma channel 4 Input gamma channel 3 Input gamma channel 2 Input gamma channel 1 PIN FUNCTION
Block Diagram
VS+
EL5623
COLUMN DRIVER
3
FN7507.1 May 6, 2005
EL5623 Typical Performance Curves
5 VS=7.5V CL=10pF RL=1k GAIN (dB) 1 RL=10k GAIN (dB) 2 10 VS=7.5V RL=10k CL=47pF CL=100pF
3
6
-1
RL=562 RL=150
-2
CL=12pF
-3
-6
-5 100
1K
10K
100K
1M
10M
100M
-10 1K
10K
100K
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 1. FREQUENCY RESPONSE FOR VARIOUS RLOAD
FIGURE 2. FREQUENCY RESPONSE FOR VARIOUS CLOAD
VS=7.5V RL=10k CL=8pF
VS=7.5V RL=10k CL=8pF VIN VIN
2V/DIV VOUT
50mV/DIV
VOUT
1s/DIV
100ns/DIV
FIGURE 3. LARGE SIGNAL TRANSIENT RESPONSE
1K OUTPUT IMPEDANCE ()
FIGURE 4. SMALL SIGNAL TRANSIENT RESPONSE
VS=5V VOLTAGE NOISE (nV/Hz)
VS=7.5V
100
100
10
BUFFER
1
0 1K
10K
100K FREQUENCY (Hz)
1M
10M
10 10K
100K
1M FREQUENCY (Hz)
10M
100M
FIGURE 5. OUTPUT IMPEDANCE vs FREQUENCY
FIGURE 6. INPUT NOISE SPECTRAL DENSITY vs FREQUENCY
4
FN7507.1 May 6, 2005
EL5623 Typical Performance Curves
20 VS=7.5V RL=1k 0 CL=1.5pF OVERSHOOT (%) PSRR+ PSRR-40 60 VS=7.5V RL=10k 50 V OPP=1V 40 30 20 10 0
PSRR (dB)
-20
-60
-80 1K
10K
100K FREQUENCY (Hz)
1M
10M
0
500
1K CLOAD (pF)
1.5K
2K
FIGURE 7. PSRR vs FREQUENCY
FIGURE 8. OVERSHOOT vs CAPACITANCE LOAD
800
POWER DISSIPATION (W)
VS=7.5V RL=10k 700 C =8pF L SETTLING TIME (ns) 600 BUFFER 500 400 300 200
1.4 1.2
JEDEC JESD51-7 - HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD
1.031W 1 0.8 0.6 0.4 0.2 0 0 25 50 75 85 100 125
JA
SO =9 P16 7 C/ W
TS
2
3
4 STEP SIZE (+V)
5
6
AMBIENT TEMPERATURE (C)
FIGURE 9. SETTLING TIME vs STEP SIZE
FIGURE 10. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
0.9 0.8 POWER DISSIPATION (W)
JEDEC JESD51-3 - LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD
0.7 676mW 0.6 0.5 0.4 0.3 0.2 0.1 0 0 25 50 75 85 100 125
TS SO 1 4 P1 6 8 C/ W
JA =
AMBIENT TEMPERATURE (C)
FIGURE 11. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
5
FN7507.1 May 6, 2005
EL5623 Description of Operation and Application Information
Product Description
The EL5623 is fabricated using a high voltage CMOS process. It exhibits rail to rail input and output capability and has very low power consumption. When driving a load of 10K and 12pF, the buffers have a -3dB bandwidth of 10MHz and exhibit 9V/s slew rate. The maximum power dissipation allowed in a package is determined according to:
T JMAX - T AMAX P DMAX = ------------------------------------------- JA
where: TJMAX = Maximum junction temperature TAMAX = Maximum ambient temperature JA = Thermal resistance of the package PDMAX = Maximum power dissipation in the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the loads, or:
P DMAX = V S x I S + i x [ ( V S + - V OUT i ) x I LOAD i ]
Input, Output, and Supply Voltage Range
The EL5623 is specified with a single nominal supply voltage from 5V to 15V or a split supply with its total range from 5V to 15V. Correct operation is guaranteed for a supply range from 4.5V to 16.5V. The input common-mode voltage range of the EL5623 is within 500mV beyond the supply rails. The output swings of the buffers typically extend to within 100mV of the positive and negative supply rails with load currents of 5mA. Decreasing load currents will extend the output voltage even closer to each supply rails.
when sourcing, and:
P DMAX = V S x I S + i x [ ( V OUT i - V S - ) x I LOAD i ]
Output Phase Reversal
The EL5623 is immune to phase reversal as long as the input voltage is limited from VS- -0.5V to VS+ +0.5V. Although the device's output will not change phase, the input's over-voltage should be avoided. If an input voltage exceeds supply voltage by more than 0.6V, electrostatic protection diode placed in the input stage of the device begin to conduct and over-voltage damage could occur.
when sinking. where: i = 1 to total number of buffers VS = Total supply voltage of buffer and VCOM ISMAX = Total quiescent current VOUTi = Maximum output voltage of the application ILOADi = Load current of buffer If we set the two PDMAX equations equal to each other, we can solve for the RLOAD's to avoid device overheat. The package power dissipation curves provide a convenient way to see if the device will overheat. The maximum safe power dissipation can be found graphically, based on the package type and the ambient temperature. By using the previous equation, it is a simple matter to see if PDMAX exceeds the device's power derating curves.
Output Drive Capability
The EL5623 does not have internal short-circuit protection circuitry. The buffers will limit the short circuit current to 120mA if the outputs are directly shorted to the positive or the negative supply. If the output is shorted indefinitely, the power dissipation could easily increase such that the part will be destroyed. Maximum reliability is maintained if the output continuous current never exceeds 30mA, a limit is set by the design of the internal metal interconnections.
The Unused Buffers
It is recommended that any unused buffers should have their inputs tied to ground plane.
Power Supply Bypassing and Printed Circuit Board Layout
As with any high frequency device, good printed circuit board layout is necessary for optimum performance. Ground plane construction is highly recommended, lead lengths should be as short as possible, and the power supply pins must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the VS- pin is connected to ground, one 0.1F ceramic capacitor should be placed from the VS+ pin to ground. A 4.7F tantalum capacitor should then be connected from the VS+ pin to ground. One 4.7F capacitor may be used for multiple devices. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used.
Power Dissipation
With the high-output drive capability of the EL5623, it is possible to exceed the 125C "absolute-maximum junction temperature" under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for the application to determine if load conditions need to be modified for the buffer to remain in the safe operating area.
6
FN7507.1 May 6, 2005
EL5623
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 7
FN7507.1 May 6, 2005

▲Up To Search▲

Price & Availability of EL5623IRZ-T7

	To Download EL5623IRZ-T7 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .